1. Field of the Invention
The present invention relates to a field programmable gate array having a memory that uses a write-port enable signal.
2. Description of the Prior Art
An integrated circuit field programmable gate array (FPGA) comprises an array of programmable logic cells (PLCs). Each PLC includes a programmable logic block, which is referred to herein as a programmable function unit (PFU), but may also be referred to as a programmable logic unit (PLU) or by various other names known in the art. The logic cells also include conductors, conventionally referred to as "routing resources", for routing signals within, and between, the various PLCs of the FPGA. The routing resources are also typically programmable to some extent, in order to provide additional flexibility for implementing the desired functionality by the user of the FPGA. See, for example, U.S. Pat. No. 5,384,497 co-assigned herewith for routing resource techniques known in the art.
The PFU includes various programmable logic elements that may be programmed by the user to provide a wide variety of possible logic functions by a single integrated circuit (IC). The logic elements are typically implemented in part by the use of a programmable look-up table (LUT) that comprises an array of memory cells. One implementation of the use of look-up tables in logic elements is shown in U.S. Pat. No. 5,386,156 co-assigned herewith. It is also known to use the memory cells in the LUT as user-accessible random access memory (RAM), which may be accessed by various other logic cells in the FPGA. This provides the flexibility of using a given PLC to perform either logic or memory functions, as may be programmed by the user of the FPGA. The RAM control signals include a write-strobe signal which is activated when data is to be written into the RAM. In addition, a read-port enable signal is activated when data is to be read out of the RAM. In a typical memory implementation, only one write location and only one read location (which may be the same as the write location) of the RAM may be accessed at any given time. One implementation of such a programmable dual-use for memory cells is given in U.S. Pat. No. 5,343,406, for example.
Referring to FIG. 1, an illustrative random access memory (RAM) that comprises the memory cells in four programmable function units 101 (PFU1), 102 (PFU2), 103 (PFU3) and 104 (PFU4) is shown. Each PFU comprises 64 memory cells, with various other numbers of memory cells and PFUs in a given RAM being possible. Each PFU in the RAM includes a write-strobe signal input (lines 105, 106, 107 and 108) that allows data to be written into the PFU from input lines 132. A read-port enable signal, also known as the output tri-state signal "T", is supplied to each tri-state output buffer(109, 110, 111 and 112) on signal lines 113, 114, 115 and 116. When activated, a given read-port enable signal allows the associated tri-state output buffer to place data read from the associated PFU onto the associated conductor of the DATA OUT bus (117). Note that the read-port enable signals from 2-to-4 decoder 122 are ANDed by the AND gates 118, 119, 120 and 121 with the write-enable signal on line 123 to produce the above-noted write-strobe signals on lines 105-108. The address lines 124 comprise six address bits (addr[5:0]). Two of the address lines (125, 126) connect the upper address bits (addr[4] and addr[5]) to the decoder 122, whereas four lines (bus 127) connect the lower address bits (addr[3:0]) directly to the RAM logic block (PFU1, PFU2, PFU3 and PFU4). These upper address bits (addr[4] and addr[5]), being those that are not connected directly to the address input lines (127) of the RAM logic block, must be decoded to provide the read-port enable signals that determine which PFU in the RAM logic block to enable at a given time.
It can be seen that the number of address lines that connect directly to a given PFU is dependent on the number of RAM bits in each PFU. In the example shown in FIG. 1, four address lines (addr [3:0]) are required to decode sixteen RAM bits, since 2.sup.4 =16. It can also be seen that the prior-art FPGA requires separate decoding for the write-strobe and read-port enable signals when the size of the RAM to be implemented is larger than the size supported by each PFU. It can also be seen that in the illustrative 64.times.4 RAM (64 address bits and 4 data lines) of FIG. 1, a total of four AND gates (118, 119, 120, 121) and nine control signal lines (i.e., the write-enable 123, four write-strobes 105, 106, 107 and 108, and four read-port enables 113, 114, 115 and 116 are required, in addition to the other circuitry illustrated. Furthermore, the AND gates are implemented in another PFU that is additional to the ones shown in FIG. 1.